Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results

This paper presents the implementation and results of the test suite for DSM ASIC consisting of static, ∆Iddq, and dynamic patterns based on scan, and quantitatively reports the advantages of dynamic pattern over AC static pattern, even at a low frequency, and advantages of ∆Iddq test over traditional Iddq. A defect level calculation method is presented which decomposes the defect level into, and considers interaction between, static, ∆Iddq, dynamic, and memory BIST defects. Defect density and defect level are also reported based on the new method.